Pattern Test

Diagram

Setup

TTCci was setup to deliver clock (via TTCex) to both DTTF and GT crates.

Patterns were generated in the WS module. BS module transmited the patterns in an asynchroneous way to its SCSI output connectors. Delays of the BS and WS clock had to be tuned to obtain correct results.

On the GMT side, spy memories of the InputFPGAs were read using standalone gmt.exe program (test function GMTINxSpyTest).

Results

BS outputs were consistent with generated patterns. A few bit errors were identified on the GMT inputs.

Muon Test

Diagram

Setup

TTCci was setup to deliver clock (via TTCex) to both DTTF and GT crates. B-channel was setup to broadcast a BC0 signal. The orbit output of the TTCci was connected to the DTTF system.

Track fragments generated with ORCA were loaded to DIO test modules in a separate 6U crate. A set corresponding to 396 bx was repeated to fill an orbit (3564 bx) 9 times and start at the same place at each orbit. They were transmitted to PHTF modules which combined them into tracks. Resulting tracks were sent to WS and BS modules. Delays of 0x30-0x40 (out of 0x64) had to be set on WS and BS to guarantee correct data transmission.

On the GMT side, spy memories of InputFPGAs were read using standalone gmt.exe program (test function GMTINxSpyTest and GMTInterfaceBitErrorTest) synchroneosly with the BC0.

Results

The quality of the data arriving at GMT was very sensitive to delays at every element of the chain (DIO, PHTF, WS, BS). The size of the resulting stability window was relatively small. Bad-data window on WS was 0x50-0x10 (whole range is 0x64) at the 0x40 delay on BS. With the best setting the bit-error rate was few errors per hour. The DIO memories seem to be unstable against the electrical activity on the test platform.

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Last updated by Ivan Mikulec on 29 Jan 2007